NEC and ParityQC collaborate to develop highly-scalable, practical quantum computers
Tokyo, Japan & Innsbruck, Austria, February 10, 2021 – NEC Corporation (NEC; TSE: 6701) and ParityQC today announced that they have started collaborating in the field of quantum annealing, a method of quantum computing. NEC will be the first company worldwide (*1) implementing the ParityQC architecture for quantum annealing devices.
The collaboration entails NEC implementing the ParityQC Architecture (*2), ParityQC’s new paradigm on how to solve optimization problems on a quantum computer, into its own superconducting parametron quantum devices (*3). This will pave the way for highly-scalable, practical quantum annealers capable of solving large-scale combinatorial optimization problems such as financial portfolio optimization and manufacturing planning. NEC aims to develop such quantum annealers for practical use by 2023.
The combination of ParityQC’s software, which ensures a compact encoding of industry-relevant problems, and the architecture’s capabilities allow organizations to benefit by performing larger computations. Realizing quantum devices using the ParityQC architecture provides a path to resolving challenges on the route to practical large scale quantum annealers.
ParityQC architecture built with NEC’s superconducting parametrons
NEC, partially supported by Japan’s New Energy and Industrial Technology Development Organization (NEDO), is now developing quantum annealers using superconducting parametron qubits and working on increasing the number of all-to-all connected qubits, with an aim to realize practical machines by 2023. NEC will apply the results of the collaboration with ParityQC to the ongoing project with NEDO.
Masayuki Shirane, Senior Manager, System Platform Research Laboratories, NEC Corporation, said, “I’m thrilled about this partnership in quantum computing research with ParityQC. I firmly believe that using the ParityQC architecture will enable us to realize a quantum annealing machine that delivers the full potential of our superconducting parametron qubits.”
Magdalena Hauser & Wolfgang Lechner, CEOs of ParityQC, said, “One of the great advantages of simultaneously developing hardware and software is the perfect alignment of both disciplines. Exploring this approach together with NEC’s newly developed hardware platform holds great promise.”
NEC researchers assembling their next-generation quantum annealing device based on the ParityQC architecture (*This quantum annealing device is based on results obtained from a project commissioned by the New Energy and Industrial Technology Development Organization (NEDO))
*1) According to NEC research, as at February 10, 2021.
*2) The ParityQC Architecture (based on the LHZ scheme) represents a completely new paradigm on how to solve optimization problems on a quantum computer. The architecture delivers a blueprint (instructions set and chip layout) for quantum computers that enables hardware developers to build fully programmable, parallelizable and scalable chips with a greatly reduced complexity. The LHZ scheme was first proposed by Lechner, Hauke and Zoller, see https://advances.sciencemag.org/content/1/9/e1500838
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